FIG. 7A is a block diagram showing a main portion of a solid state image pickup apparatus assembling a solid state imaging pickup device, and FIGS. 7B and 7C are schematic plan views showing the structure of the solid state image pickup device. FIG. 7D is a schematic cross sectional view showing a portion of a pixel area of a solid state image pickup device.
Referring to FIG. 7A, the structure of a solid state image pickup apparatus will be described. A solid state imaging pickup device 51 generates signal charges corresponding to an amount of light incident upon each pixel and supplies an image signal corresponding to the generated signal charges. A drive signal generator 52 generates drive signals (transfer voltage, etc.) for driving the solid state image pickup device 51 and supplies them to the solid state image pickup device 51. An analog front end (AFE) 53 subjects an output signal from the solid state imaging unit 51 to correlation double sampling, amplifies the sampled signal at an externally set gain, converts it into a digital signal, and outputs the digital signal. A digital signal processor (DSP) 54 processes an image signal supplied from the analog front end 53, such as recognition process, data compression and network control, and outputs the processed image data. A timing generator (TG) 55 generates timing signals for the solid state image pickup device 51, drive signal generator 52 and analog front end 53, to control the operations thereof. The drive signal generator 52 includes, for example, a V driver for generating a vertical charge coupled device (CCD) drive signal. Signals supplied from the drive signal generator 52 to the solid state image pickup device 51 include a horizontal CCD drive signal, a vertical CCD drive signal, an output amplifier drive signal and a substrate bias signal.
As shown in FIG. 7B, the solid state image pickup device is constituted of: a plurality of photosensors 62 disposed, for example, in a matrix shape; a plurality of vertical CCDs 64 disposed near each column of the photosensors 62; a horizontal CCD 66 electrically connected to the vertical CCDs via a V drain area 68; and an amplifier circuit 67, connected to an output terminal of the horizontal CCD 66, for amplifying an output charge signal from the horizontal CCD 66. A pixel area 61 is constituted of the photosensors 62 and vertical CCDs 64.
The photosensor 62 is constituted of a photosensitive element, e.g., a photoelectric conversion element (photodiode) and a read gate. The photoelectric conversion element generates signal charges corresponding to an incidence light amount and accumulates them. Reading the accumulated signal charges to the vertical CCD (vertical transfer channel) 64 is controlled by a voltage applied to the read gate. The signal charges read to the vertical CCD 64 are transferred in the vertical CCDs (vertical transfer channel) 64 toward the horizontal CCD 66 (in a vertical or column direction).
Signal charges transferred from the bottom ends of the vertical CCDs 64 via a V drain area (vertical CCD drain area) 68 are transferred in the horizontal CCD (horizontal transfer channel) 66 in a horizontal direction (called also row direction), amplified by the amplifier circuit 67 and output to an external. The V drain area 68 has drains 95 and will be later described in detail.
The photosensors 62 are disposed in a square matrix layout at a constant pitch in the row and column directions as shown in FIG. 7B, or disposed in a honeycomb layout in the row and column directions by shifting every second photosensors, for example, by a half pitch.
FIG. 7C is a schematic plan view of a solid state image pickup device having the honeycomb layout. The honeycomb layout has photosensors 62 disposed in a first square matrix layout and photosensors 62 disposed in a second square matrix layout at positions between lattice points of the first square matrix layout. Vertical CCDs (vertical transfer channels) 64 are disposed in a zigzag way between photosensors 62. Although this layout is called a honeycomb layout, the photosensor 62 of most honeycomb layouts is octangular.
As shown in FIG. 7D, formed in a p-type well 82 formed in a semiconductor substrate 81, e.g., an n-type silicon substrate, are a charge accumulation region 71 made of an n-type impurity doped region, a p+-type buried region 71a formed on the photoelectric conversion element, and a vertical transfer channel 73 made of an n-type region disposed next to the photoelectric conversion element and buried region. The n-type charge accumulation region 71 and an underlying p-type region constitute a photoelectric conversion element. The photoelectric conversion element generates signal charges corresponding to an incidence light amount. The generated signal charges are accumulated in the charge accumulation region 71. A read gate 72 is defined between the charge accumulation region 71 and vertical transfer channel 73. A vertical transfer electrode 75 is formed above the vertical transfer channel 73, with an insulating film 74 being interposed therebetween. A p-type channel stop region 76 is formed between adjacent charge accumulation regions 71.
The channel stop region 76 is used for electrically isolating the charge accumulation regions 71, vertical transfer channels 73 and the like. The insulating film 74 is a silicon oxide film formed on the surface of the semiconductor substrate 81, for example, by thermal oxidation. The vertical transfer electrode 75 is constituted of first and second vertical transfer electrodes made of, for example, polysilicon. The first and second vertical transfer electrodes may be made of amorphous silicon. In accordance with voltages (drive signals) applied to the vertical transfer electrode 75, signal charges are transferred in the vertical transfer channel 73. The vertical transfer electrode 75 above the read gate 72 has also the function of reading signal charges accumulated in the charge accumulation region 71, from the read gate 72 to the vertical transfer channel 73 in accordance with an applied voltage (drive signal). An insulating silicon oxide film 77 is formed on the vertical transfer electrode 75, for example, by thermally oxidizing polysilicon. The vertical CCD 64 is constituted of the vertical transfer channel 73, upper insulating film 74 and vertical transfer electrode 75.
A light shielding film 79 of, e.g., tungsten, is formed above the vertical transfer electrode 75, with the insulating silicon oxide film 77 being interposed therebetween. Openings 79a are formed through the light shielding film 79 at positions above the charge accumulation regions 71. A silicon nitride film 78 is formed on the light shielding film 79; The silicon nitride film 78 is not necessarily required.
As described above, the light shielding film 79 has the openings 79a above the charge accumulation regions 71 and prevents light incident upon the pixel area 61 from entering the region other than the photoelectric conversion elements.
A planarized layer 83a made of, e.g., borophosphosilicate glass (BPSG) is formed above the light shielding film 79. On this planarized surface, a color filter layer 84 is formed which is of three primary colors: red (R), green (G) and blue (B). Another planarized layer 83b is formed on the color filter layer 84. On the planarized layer 83b having a planarized surface, micro lenses 85 are formed, for example, by melting and solidifying a photoresist pattern of micro lenses. Each micro lens 85 is a fine hemispherical convex lens disposed above each charge accumulation region 71. The micro lens 85 converges incidence light to the photoelectric conversion element. Light converged by one micro lens 85 passes through the color filter layer 84 of one of the red (R), green (G) and blue (B) and becomes incident upon one photoelectric conversion element. Therefore, the photoelectric conversion elements include three types of photoelectric conversion elements: photoelectric conversion elements upon which light passed through the red (R) color filter layer 84 becomes incident; photoelectric conversion elements upon which light passed through the green (G) color filter layer 84 becomes incident; and photoelectric conversion elements upon which light passed through the blue (B) color filter layer 84 becomes incident.
FIGS. 8A and 8B are schematic diagrams illustrating a manufacture method for a solid state image pickup device.
Referring to FIG. 8A, a semiconductor substrate 81, e.g., an n-type silicon substrate, is prepared and p-type impurities, e.g., boron ions, are implanted to form a p-type well 82.
In a surface layer of the well 82, n-type impurities, e.g., phosphorus or arsenic ions, are implanted to form a vertical transfer channel 73, and p-type impurities, e.g., boron ions, are implanted to form a channel stop region 76. An insulating film 74 is formed on the semiconductor substrate 81, the insulating film being an oxide-nitride-oxide (ONO) film including a thermally oxidized silicon oxide film, a silicon nitride film formed through chemical vapor deposition (CVD) and a silicon oxide film formed by thermally oxidizing the surface of the silicon nitride film. The silicon nitride film in the insulating film 74 has a function of an oxygen intercepting film.
A vertical transfer electrode 75 made of, for example, polysilicon, is formed covering the vertical transfer channel 73. The vertical transfer electrode 75 is made of, for example, first and second charge transfer electrodes. Signal charges generated in the photoelectric conversion elements are transferred in the vertical direction by controlling the potential of the vertical transfer channel 73. The vertical transfer electrode 75 is formed by depositing polysilicon on the insulating film 74, for example, by CVD and patterning it through photolithography and etching.
By using the vertical transfer electrode 75 as a mask or by using a resist pattern formed by coating resist on the surfaces of the vertical transfer electrode 75 and insulating film 74 and exposing and developing the resist, n-type impurities, e.g., phosphorus or arsenic ions, are implanted to form a charge accumulation region 71. A buried layer 71a is formed on the charge accumulation region 71 by implanting p-type impurities, e.g., boron ions. A p-type region defined between the charge accumulation region 71 and vertical transfer channel 73 is a read gate 72. The vertical transfer electrode 75 is thermally oxidized to form a silicon oxide film 77 on the surface thereof. Photoelectric conversion elements (charge accumulation regions 71) may be disposed in the square matrix layout or in the honeycomb layout.
Although not shown in the cross sectional view of FIG. 8A, a horizontal CCD 66 and a V drain area 68 are formed on the semiconductor substrate 81 by the processes partially including the above-described processes. For example, by using the same process as the process of forming the first layer vertical transfer electrode in the pixel area, a first layer vertical transfer electrode is formed in the V drain area, and by using the same process as the process of forming the second layer vertical transfer electrode in the pixel area, a gate control electrode in the V drain area is formed above the first vertical transfer electrode. An amplifier 67 and the like are also formed. The V drain area will be described later more in detail.
Referring to FIG. 8B, a light shielding film 79 of, for example, tungsten, is formed above the silicon oxide film 77. Resist is coated on the light shielding film 79, exposed and developed to leave the resist in predetermined areas. By using this resist as a mask, the light shielding film 79 is etched to form an opening 79a above each charge accumulation region 71.
A silicon nitride film 78 is formed covering the light shielding film 79, and then a planarized layer 83a of BPSG is formed, for example, by CVD. For example, a deposited BPSG film is reflowed at 850° C. to form the planarized layer 83a. In addition to reflow, planarization may be performed, for example, by chemical mechanical polishing (CMP). Instead of BPSG, silicon oxide doped with impurities to lower a melting point may also be used.
On the planarized surface of the planarized layer 83a, a color filter layer 84 of three primary colors of red (R), green (G) and blue (B) is formed. For example, the color film layer 84 is formed by coating photoresist liquid mixed with granular pigment (pigment dispersed resist liquid) on the surface of the planarized layer 83a, exposing and developing it and curing it at a curing temperature of 220° C. Filter layers of three colors of red (R), green (G) and blue (B) are sequentially formed.
A planarized layer 83b is formed on the color filter layer 84 because the surface of the color filter layer 84 is irregular. For example, the planarized layer 83b is formed by coating material having the similar composition as that of transparent resin and curing it at a curing temperature of 220° C. Next, micro lenses 85 are formed on the planarized layer 83b. 
FIGS. 9A and 9B are a schematic plan view and a schematic cross sectional view illustrating the V drain area 68.
Referring to FIG. 9A, as described earlier, the V drain area 68 is disposed adjacent to the pixel area 61 on a downstream side of the signal charge vertical transfer direction of the pixel array (between the pixel area 61 and horizontal CCD).
The V drain area 68 has a V drain (vertical CCD drain) 68a having a function of sweeping out, at high speed, charges excessively generated in the photosensors 62, residual charges in the photosensors 62, vertical transfer channels 73 and the like, and unnecessary charges generated in the area other than the pixel area. The V drain 68a has a drain 95 of an n-type impurity doped region disposed, for example, at each column of the photosensors 62. The drain 95 is formed near at the vertical transfer channel 73 extending from the pixel area 61. In the V drain 68a, a gate control electrode 99 is formed covering the first layer vertical transfer electrode 75b. 
FIG. 9B is a cross sectional view taken along line 9B-9B shown in FIG. 9A. Unnecessary charges are moved from the vertical transfer channel 73 to the drain 95 via the gate 94. The gate 94 is a barrier region defined between the vertical transfer channel 73 and drain 95. The potential of the gate 94 is controlled by a voltage (sweeping voltage) applied to the gate control electrode 99. Unnecessary charges are drained (swept) into the drain 95. The unnecessary charges swept (moved) into the drain 95 are ejected outside the V drain 68a via a metal wiring 96. The metal wiring 96 is electrically connected to a contact 100 of the drain 95.
In order to simplify the drawing, the structure between the gate control electrode 99 and metal wiring 96 is omitted. The structure includes, similar to the structure shown in FIG. 7D, the silicon oxide film 77 on the gate control electrode 99, upper light shielding film 79 with the openings 79a, upper silicon nitride film 78 and planarized layer 83a. 
The voltages applied to constituent elements are approximately as in the following. A power source voltage of about 15 V is applied to the drain 95, metal wiring 96 and gate control voltage 99. A pulse voltage of about 0 V to −10 V is applied to the first layer vertical transfer electrode 75b for signal charge transfer.
A solid state image pickup device having a V drain 68a can perform an operation necessary for high speed signal charge drive, such as consecutive photographing.
An insulating film 74 of the V drain 68a is formed by the same process as the process of forming the insulating film 74 in the pixel area 61. Similar to the pixel area, the insulating film (formed on the surface of the semiconductor substrate 81 and under the first layer transfer electrode 75b) of the V drain 68a adopts the ONO structure of the silicon oxide film (bottom oxide film) 74a, silicon nitride film 74b and silicon oxide film (top oxide film) 74c. 
Unnecessary charges, partially hot electrons, accelerated by a high electric field generated by a sweeping voltage are trapped at the interface between the silicon nitride film 74b and silicon oxide film 74a, which may induce a variation (temporal change) in the sweeping voltage. If a solid state image pickup device is used in a long term, there may arise the problem of lowering a sweeping performance, and hence lowering the performance and quality of the solid state image pickup device.
FIGS. 10A to 10C are schematic cross sectional views illustrating a manufacture method for the V drain 68a. 
Referring to FIG. 10A, ion implantation same as the ion implantation into the pixel area 61 described with reference to FIG. 8A, is performed to form a p-type well 82 and an n-type vertical transfer channel 73. A drain 95 of an n-type impurity region is formed by implanting, for example, phosphorus or arsenic ions. A p-type region between the vertical transfer channel 73 and drain 95 is a gate 94. By using the same process as the process of forming the insulating film 74 in the pixel area 61, an ONO film is formed covering the vertical transfer channel 73, gate 94 and drain 95. The ONO film is constituted of a silicon oxide film (bottom oxide film) 74a, a silicon nitride film 74b and a silicon oxide film (top oxide film) 74c. 
A polysilicon film heavily doped with phosphorus is deposited on the ONO film and patterned by anisotropic reactive ion etching using a resist pattern formed by photolithography to thereby form a firs layer vertical transfer electrode 75b. 
Referring to FIG. 10B, after the resist pattern is removed, an insulating film 80 is formed by thermally oxidizing the surface of the first layer vertical transfer electrode 75b. The insulating film 80 electrically insulates the first layer vertical transfer electrode 75b from a gate control electrode to be formed next.
Referring to FIG. 10C, a polysilicon film heavily doped with phosphorus is deposited and patterned by anisotropic reactive ion etching and photolithography to thereby form a gate control electrode 99 above the first vertical transfer electrode 75b. The first layer vertical transfer electrode 75b and the insulating film 80 on the electrode 75b in the V drain are formed by the same process as the process of forming those in the pixel area 61, and the gate control electrode 99 is formed by the same process as the process of forming the second layer vertical transfer electrode 75c in the pixel area 61. The gate control electrode 99 in the V drain 68a is formed covering the gate 94.
Although not shown, as described earlier, a silicon oxide film 77 is formed on the gate control electrode 99. A light shielding film of tungsten is formed on the silicon oxide film, and openings are formed through the light shielding film by using a resist pattern. A silicon nitride film and a planarized layer are formed on the light shielding film.
For example, by using a resist pattern, a contact hole is formed by reactive ion etching, extending from the surface of the planarized layer to the drain 95. A contact 100 of a high concentration n-type impurity region is formed in the drain 95 by implanting n-type impurities, e.g., arsenic ions, via the contact hole. A metal wiring 96 is formed being electrically connected to the contact 100 in the drain 95 via the contact hole.
An invention aiming to provide a solid state image pickup device is disclosed which device is stable, highly reliable, thin, and high in breakdown voltage and can suppress a temporal change in the read voltage to be caused by hot electrons (e.g., refer to Japanese Patent Laid-open Publication No. 2003-332556).
The solid state image pickup device according to the invention described in Japanese Patent Laid-open Publication No. 2003-332556, includes photoelectric conversion elements formed in a semiconductor substrate and an insulating film above a vertical transfer channel near the photoelectric conversion elements. The insulating film has a lamination structure of silicon oxide films and a silicon nitride film. At least the silicon nitride film of the insulating film does not extend near to the upper end portion of the photoelectric conversion element.